1. Field of the Invention
The present invention relates to a master communication circuit, a slave communication circuit, and a data communicating method.
2. Description of the Related Art
When debugging an integrated circuit equipped with a microcomputer, debug data must be written into the integrated circuit to be debugged or data output by the microcomputer must be read out. Therefore, the integrated circuit needs an interface for inputting and outputting data as above.
By the way, it is important for integrated circuits to reduce the chip size thereof as much as possible for cost reduction, etc. Therefore, it is especially desirable to reduce terminals used for inputting and outputting the debug data as much as possible. A one-line communication mode is therefore proposed which uses one input/output terminal for data input/output to transmit/receive data through one communication line connected to this input/output terminal. For example, the Universal Asynchronous Receiver/transmitter (UART) disclosed in Published Japanese Translation of a PCT application No. 2001-508562 is known as such a one-line communication mode.
In the UART, data are transmitted and received between a master communication circuit and a slave communication circuit connected through one communication line. In the UART, one-bit data (“1” or “0”) are transmitted and received between the master communication circuit and the slave communication circuit by changing the signal level of the communication line with the master communication circuit or the slave communication circuit.
For example, when the master communication circuit transmits data to the slave communication circuit, the master communication circuit drives the signal level of the communication line to “0”. The master communication circuit subsequently drives the signal level of the communication line to “1” if the data to be transmitted is “1” or maintains the signal level of the communication line to “0” without change if the data to be transmitted is “0”. The slave communication circuit acquires the signal level of the communication line after a predetermined time has elapsed from the start of the data transmission/reception to receive “1” or “0”.
For example, when the master communication circuit receives data from the slave communication circuit, the master communication circuit drives the signal level of the communication line to “0”. The master communication circuit subsequently drives the signal level of the communication line to “1”. The slave communication circuit maintains the signal level of the communication line to “1” without change if the data transmitted to the master communication circuit is “1” or drives the signal level of the communication line to “0” if the data transmitted to the master communication circuit is “0”. The master communication circuit acquires the signal level of the communication line after a predetermined time has elapsed from the start of the data transmission/reception to receive “1” or “0”.
As described above, in one-line communication modes such as the UART, the master communication circuit and the slave communication circuit must share time such as the timing of acquiring the signal level of the communication line. Therefore, to ensure the data transmission/reception between the master communication circuit and the slave communication circuit, deviation must be reduced between a clock used for counting time in the master communication circuit and a clock used for counting time in the slave communication circuit.
For example, in the case of the UART, the data transmitted/received between the master communication circuit and the slave communication circuit are a total of 10 bits, which are one start bit, one stop bit, and eight data bits. For example, assuming that the deviation of the clock is 5% for one bit in the master communication circuit and the slave communication circuit, the deviation of 50% may be generated in 10 bits, and the signal level of the communication line is acquired at an unintended timing. Therefore, if the UART is used, the deviation is generally required to be reduced to about 2% to 3% in the clock of the master communication circuit and the slave communication circuit.
When such a one-line communication mode is used to debug an integrated circuit equipped with a microcomputer, the debugged side, i.e., the slave communication circuit generally generates a clock for the one-line communication from the main clock of the microcomputer. Since different circuits have different main clock frequencies, it is difficult to generate an accurate clock for all the main clocks having different frequencies. Therefore, although an oscillator for generating a communication clock is needed in addition to the main clock of the microcomputer to increase the accuracy of the clock of the slave communication circuit, it is not practical to dispose an oscillator for debugging.